Single crystal high dielectric constant material and method for making same

ABSTRACT

The invention provides a stable oxide material system for a capacitor, electronic device or a memory device having an effective high-k value with an effective zero alpha while exhibiting low leakage current density. The stable oxide material comprises M x -Si1-xO2, wherein the elements M &amp; Si are mixed such that the insulator layer comprises staggered edge-linked SiO2-MO2 bonding chains to provide a stable 3-dimensional single crystal system.

FIELD OF THE INVENTION

The invention relates to a high dielectric material. In particular theinvention relates to a low temperature deposited high-k dielectricmaterial for Metal-Insulator-Metal (MIM) capacitor applications with anadditional application in Metal-Insulator-Semiconductor (MIS or MOS)systems.

BACKGROUND TO THE INVENTION

A particular type of capacitor design is a Metal-Insulator-Metal (MIM)capacitor. MIM Capacitor devices are pervasively used in all modern dayelectronic devices, and in particular radio frequency and analoguecircuitry. MOS capacitor structures are an integral part of MOSField-Effect Transistors (MOSFETs) used extensively in digitalcircuitry. Portable consumer and communication devices are drivingminiaturisation of these devices along with ultra lower powerconsumption requirements to extend battery life.

Miniaturisation of digital components has centred on the scaling ofMOSFET devices, and this has been achieved so far with the introductionof metal gate/high-k/Si MOS structures. Nevertheless, future scalingwill likely require the replacement of Si with a higher mobilitysemiconductor like Ge and/or In_(0.53)Ga_(0.47)As in combination withalternative architecture (e.g. trigate MOSFET, junctionless MOSFET,etc.), introducing different problem issues in controlling deviceperformance. One problem with high-k materials is the capacitancehysteresis observed for high-k material systems, causing variability inthe electrical characteristics and thereby directly affecting deviceperformance.

Miniaturisation of RF and analog components is a real problem in theelectronics industry. Four key requirements of a dielectric in thedesign of a capacitor device are to: (i) aim for a low frequencycapacitance density as high as possible at zero DC bias; (ii) have aslow a leakage current density as possible at the device operatingvoltage to ensure reliable operation; (iii) have as high a breakdownvoltage (BV) as possible for a given thickness (Electric Field Breakdown[MV/cm]), preferably at twice the operating voltage; and (iv) havenegligible charge trapping (negligible Capacitance-Voltage hysteresis).

The behaviour of capacitance with applied DC bias is measured using(C_(max)−C_(min))/C_(min)=C_(dif)=αV²+βV+c, where C_(min) is the minimummeasured capacitance, C_(max) is the capacitance at the maximum appliedvoltage, α is the quadratic voltage coefficient of capacitance, β is thelinear voltage coefficient of capacitance, and c is a constantaccounting for any asymmetry in capacitance about 0V.

If α were approximately ≦|50-100| ppm/V², the capacitor would exhibitapproximate linear rather than quadratic behaviour with voltage, showinga slope determined by α, since β can be reduced to zero by circuitdesign methods, hence α is the determining factor whether capacitancevaries with applied voltage. Units for measuring α are ppm/V² when β=0;but when β≠0 then the units for measuring β are ppm/V, since C_(dif), α,and β are constants.

An additional requirement for many capacitor applications is that thecapacitor exhibit linear capacitance behaviour with respect to theapplied voltage, as a large non-linearity creates detrimental harmonicsin electronic circuits, especially at high frequencies, as well as othernon-ideal effects. A measure of this linearity is α, since β and c canbe made to equal zero through careful circuit and device design.

For these same applications, capacitance should also remain linear asthe temperature and frequency change: α(T_(max))−α(T_(min))≦|100|units/K, and α(F_(max))−α(F_(min))≦1% units per decade, respectively.There are also many capacitor applications for which this linearity ofcapacitance with voltage, temperature, and frequency is not required. Todate, for a given relative permittivity (k) and oxide thickness (t),higher capacitance has been achieved by using larger area capacitors,since C=kε₀A/t, where C is capacitance, ε₀ is a constant (thepermittivity of free space), and A is the area of the capacitor. Therequirement of large area for the capacitors prevents any significantreduction in the surface footprint size of analogue circuitry.

Reducing the oxide thickness (t) of the capacitor could in theoryachieve the same capacitance (C) for a smaller capacitor area (A) for agiven k, but this would detrimentally increase the leakage current andreduce the breakdown voltage of the capacitor.

The ideal solution for surface planar capacitors would be to increasethe relative permittivity (k) of the oxide and reduce the area (A) forthe same oxide thickness (t) to achieve the same or greater capacitance(C). However, to date this approach has been undermined by the highleakage and low breakdown voltages associated with high-k dielectrics,demonstrating high-k MIM devices but with unacceptable leakage andbreakdown characteristics. Such structures also generally exhibit a higha value. Some high-k materials require annealing to achieve the highestk-value, and this can also contribute to higher leakage and lowerbreakdown voltages.

In addition, high-k materials are generally ionic systems and tend tohave a significant density of charge trapping sites and therefore asignificant hysteresis, which can be improved by selective depositiontechniques, processing, and annealing but not entirely removed. Chargetrapping, and the associated electrical variability, remain seriousproblems for high-k dielectrics.

Present MIM capacitors with control of a and hysteresis rely on lowk-value and covalently bonded systems such as silicon oxide, siliconnitride, or silicon oxynitride dielectrics (k˜4-6), as these oxides alsoallow control of the leakage and breakdown characteristics. A maximumcapacitance is achieved through the use of large area capacitors.Minimal hysteresis is achieved through careful concentration ratioselections, processing and annealing.

Increased capacitance with reduced surface area can be achieve throughstacking capacitors on top of each other in a 2-dimensional way andconnecting in parallel. If the number of dielectric layers is n, thenC=n×kε₀A/t, and the same capacitance can be achieved with reduced area.In reality there is a limit to the number of layers achievable due toprocessing constraints on conformal growth and connectivityrequirements, and typical values of n are ≦4. MIM capacitors with high-kmaterials can also be made in this way permitting further scaling.

Another way to increase capacitance is by making 3-dimensional MIMcapacitors inside trenches etched into silicon and surface treated toobtain an SiO₂ isolation layer. Conformal growth methods could then beused to grow single or stacked layers of metal-insulator-metalstructures. This method permits the possibility of the area beingincreased to as large as possible alongside n and k in C=n×kε₀A/t. Forthis scenario it is the capacitor footprint on the surface that isminimised, not the device area. In reality, most deposition methods inindustry have serious constrictive difficulties in making these type ofcapacitors. MIM capacitors with high-k materials can also be made inthis way using conformal growth methods, permitting further scaling.

US patent publication number US 2006 0281264 A1, assigned to MatsushitaElectric Industrial Co. Ltd., describes a gate insulator on asemiconductor substrate having a plurality of oxide layers perpendicularto the semiconductor surface and associated with respective phases.

The US patent publication discloses three stable layers formed from theALD|CVD of SiO₂, MSiO₄, and MO₂ stable phases (M=Hf|Zr). However,problems with this approach are: (i) that an unstable interface isformed between the SiO₂ layer and the claimed MSiO₄ layer; (ii) thethickness of the amorphous SiO₂ layer increasing with time taking SiO₂from the claimed MSiO₄ layer; and (iii) the claimed MSiO₄ layer actuallymoves increasingly towards a crystalline MO₂ concentration with time.Namely, the claimed MSiO₄ layer will reduce in SiO₂ concentration withtime, and exhibit spontaneous phase separation to form amorphous SiO₂and crystalline MO₂ (M_(x)Si_(1-x)O₂, x=0.5→x=1.0) with time.

The deposition of a higher x concentration M_(x)Si_(1-x)O₂ (M=Hf|Zr,x>0.5) will ensure a nucleation and growth phase separating structuredue to two factors: (i) the deposited oxide (from bulk theory) will beintrinsically metastable at such x concentrations (not stable), and (ii)the oxide is deposited on SiO₂ ensuring the growth of SiO₂ from Si and Osupplied by the decomposition of the M_(x)Si_(1-x)O₂ oxide.

Hence, phase separation is driven by the unstable bottom interface withamorphous SiO₂, the bulk phase separation and forming of amorphous SiO₂and crystalline MO₂ clusters, and the changing x concentration to formamorphous SiO₂ and crystalline MO₂ (M_(x)Si_(1-x)O₂, x>0.5→x=1.0) withtime.

It is clear that a MIM or MOS capacitor exhibiting such a structure ofthree stable phases claimed of SiO₂, MSiO₄, and MO₂ is neither stablewith time nor free from crystalline grain boundaries that would causehigh operating voltage leakage current densities and a low breakdownfield.

To date the research and development community have only been able tosynthesis amorphous or polycrystalline M_(x)Si_(1-x)O₂ metal silicates(0<x<1; M=Zr and/or Hf), which can be synthesised fairly easily. Ifsynthesised films form amorphous systems, including the amorphous formsof zircon and hafnon, and they are exposed to a high enough temperatureanneal in an appropriate ambient, they can be made polycrystalline.

However, the amorphous to crystalline transition does not form a singlecrystal for any significantly large crystallite length scale, butinstead forms many small crystals all oriented in different directionswith crystallite sizes very much smaller than the thickness of thefilms. The boundaries between these crystallite regions, called grainboundaries, render these dielectric films effectively useless forelectronics applications due to the very high leakage and low breakdownvoltages associated with such grain boundary rich films.

A paper publication by Ting-Ting Jiang et al., J. Phys. D: Appl. Phys.44, 185402, 1-5 (2011) a theoretical simulation which tries to comparethe electronic band gaps modelled and experimental amorphous high-kmaterials that could be used in a semiconductor device. HoweverTing-Ting Jiang does not demonstrate any type of device characteristics.The device properties referred to in the introduction section of theTing-Ting Jiang et al. paper, with respect to the ZrSiO₄ and HfSiO₄systems, are for amorphous systems only. Moreover modelling programs arenot able to model amorphous systems because of their size andcomplexity. Geological studies of crystallites in naturally formed rockgive lattice parameters for modelling crystalline systems, and thesegeological studies are the experimental results referred to in the paperfor the unit cells used in the simulations. To date no one has been ableto reproduce these materials for use in electronic devices and the priorart relates to purely amorphous or polycrystalline materials that arelimited for electronic devices.

Another publication by T. S. Böscke et al., Appl. Phys. Lett. 91, 072902(2007) reports on HfO₂ and the addition of 10% SiO₂ to form an amorphousHf_(0.9)Si_(0.1)O₂ metal silicate (x=0.9, M=Hf). The T. S. Böscke et al.paper claims that crystallisation of amorphous HfO₂ into the monoclinicform of HfO₂ after a thermal anneal leads to increased leakage and theformation of local defects. By adding 10% SiO₂ to the amorphous HfO₂, T.S. Böscke et al claim that tetragonal HfO₂ is formed instead ofmonoclinic HfO₂ during the thermal anneal process. Doping amorphous HfO₂with 10% SiO₂ and crystallising with a temperature anneal does notconstitute the formation of amorphous, or polycrystalline HfSiO₄ (x=0.5)but the formation of Hf_(0.9)Si_(0.1)O₂ (x=0.9).

A further paper by K. Kukli et al., Material Science and Engineering B109 (1-3), 2-5 (2004) reports experimental findings for two types ofsubstrate layers on which they deposit their oxide:

-   -   I. Si/SiO₂ (1.2-1.8 nm)    -   II. Si (chemically etched, nominally Si—H)

The paper refers to Hf—Si—O which has a 2:1 Hf:Si concentration ratio(x˜0.67) and is amorphous, and as such due to x and the amorphousproperties of the material suffers from the same drawbacks as describedabove.

A further publication by Lizhi Ouyang and W. Y. Ching, J. Appl. Phys. 95(12), 7918-7924 (2004) discloses a modelling paper similar to theTing-Ting Jiang paper and simulates (ZrO₂)x(SiO₂)1-x with x<0.5. Againthe simulations use the lattice parameters from geological studies ofcrystallites in rock and then substitute Zr with Si cations to getx<0.5. The experimental comparison they refer to for ZrSiO₄ or zircon isfrom experiment XPS studies on powders with x=0.5 but in an amorphous orpolycrystalline state.

An object of the invention is to provide a stable oxide material systemfor a capacitor or electronic device having an effective high-k valuewith an effective zero alpha while exhibiting low leakage currentdensity and a high electrical breakdown field.

SUMMARY OF THE INVENTION

According to the invention there is provided, as set out in the appendedclaims, capacitor device comprising:

-   -   a first layer of material;    -   a second layer of material;    -   an insulator layer of material sandwiched between the first and        second layers of the metal type materials, said insulator layer        comprise M_(x)Si_(1-x)O₂, wherein the elements M and Si are        mixed such that the insulator layer comprises staggered        edge-linked SiO₂-MO₂ bonding chains to provide a stable        3-dimensional single crystal system.

The invention combines the achievement of a high capacitance (throughachieving a high k-value) and negligible hysteresis, even withoutpost-deposition annealing, while also exhibiting excellent leakage andbreakdown characteristics. The invention improves the performance ofcurrent and future metal gate/high-k/semiconductor MOS-based devices.Achieving the correct bonding conditions is necessary at theas-deposited stage in order to achieve both the global three-dimensionalsingle crystal stability and the associated excellent electricalproperties, as described in more detail below. Man-made ZrSiO₄ or HfSiO₄systems to date have either been purely amorphous or polycrystalline,and not a single crystal structure over the thickness ranges needed forelectronic devices. Despite prior art simulations, no such bulk stable3-dimensional single crystal system for ZrSiO₄ or HfSiO₄ over lengthscales applicable to electronic devices has ever been created. Theinvention represents the first ever synthesis of single crystal zirconand hafnon at length scales comparable to the thickness of thedielectric films required in electronic devices. This holds whether thesystem is doped or undoped (N_(y), in M_(x)N_(y)Si_(1-x)O₂, with0≦y≦0.05).

The high-k material of the present invention achieves a higherdielectric constant than amorphous MSiO₄ (k˜12) because a single crystaltetragonal structure is achieved, whether doped or un-doped. This high-ksingle crystal material does not exhibit the associated problems of lowbreakdown and high leakage associated with equivalent polycrystallinesystems primarily because of the absence of grain boundaries andtherefore offers the sought-after solution. Until now no solution hasbeen found to the apparent inverse relation between k-value andoperational leakage or breakdown field, and therefore the material canaddress the needs of radio frequency micro-electromechanical systems,analogue and mixed signals products. An additional contribution to thehigh breakdown field and low leakage is the semi-covalent bonding natureof the structure, which introduces strong electron-electron bondingrather than only weak ionic bonding, and this providesquantum-mechanical exclusion regions within the material system wherecharge cannot go without providing enough energy to displace electrons.Such displacement requires larger voltages to be applied across thedielectric, thereby contributing to the reduced leakage and increasedelectrical breakdown field.

The high temperature stability of the material, alongside the high-k andother properties, for the first time offers a high-k solution that canbe fabricated at any stage in the device fabrication process, whichmeans there would be flexibility of processing, design and enhancedintegration. High temperature, high power devices to date use lower-kmaterials due to the requirement of high temperature stability of theoxide, so this breakthrough will have scaling implications for this typeof application. The present invention out-performs existingtechnologies, such as high temperature stability enabling analogue anddigital integration, reduced power consumption, negligible chargetrapping due to the high quality bulk structure; and scalability of thedielectric from hundreds of nanometres to ˜2 nanometres.

The unique bonding structure along [001], comprising staggered SiO₂-MO₂(SiO₄-MO₈, tetrahedra-dodecahedra) chains in the absence of grainboundaries, whether doped or un-doped, is an important part of the keyto achieving a combination of a high capacitor quality factor (Q), lowleakage, a high electric field breakdown, and an effective zero alphafor the bulk material system when undoped. The tetragonal symmetryallows for obtaining the highest k-value possible, and therefore thehighest capacitance density possible, in addition to the high stabilitywith voltage, frequency, and CMOS temperatures. This tetragonalsymmetry, which includes distributed and non-interacting SiO₄tetrahedra, is part the key to achieving a radiation hard material.

The invention solves the problem of obtaining a reliable, scalable, andstable high-k capacitor having all of the following as-depositedattributes: low deposition temperature; bulk linearity of capacitancebehaviour with voltage (α≦|50-100| ppm/V² or in ppm/V), temperature(units/K), and frequency (1% units per decade); or with a controllednon-linearity if selectively doped; high relative permittivity; lowleakage current density at the operating voltage (also with singledominant mechanisms at 0V—low±V and low ±V to ±breakdown voltage); highbreakdown electric field (with no soft breakdown/stress events prior tohard breakdown) at 2' the operating voltage; negligible charge trappingand negligible hysteresis (if un-doped); a low (high) capacitordissipation (quality) factor; radiation hard; thickness scalability forlow to high voltage applications; bulk stability and reliability up tohigh processing temperatures (≦1050° C.); can lead to devices withincreased speed; and reduced power consumption.

In one embodiment there is provided a capacitor device comprising

-   -   a first layer of metal type material;    -   a second layer of metal type material;    -   an insulator layer of material sandwiched between the first and        second layers of the metal type materials, said insulator layer        comprises single crystal tetragonal M_(x)N_(y)Si_(1-x)O₂        (˜0.45≦x≦˜0.55; 0≦y≦˜0.05) wherein the elements M and Si        (M=Zr|Hf or M=Hf and Zr—the material system may also contain        small doping concentrations of elements N that do not alter the        structure significantly or beyond locally but may replace M        and/or Si in some sites or may exist as oxidised interstitials.        N could be Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In.        M_(x)N_(y)Si_(1-x)O₂ is completely mixed as-deposited such that        the insulator layer comprises throughout only staggered        edge-linked SiO₂-MO₂ bonding chains along [001], or        equivalently, only staggered edge-linked SiO₄ tetrahedra (T) and        MO₈ dodecahedra (D) along [001], i.e. only T-D allowed along        [001]. There are also no T-T linkages (or SiO₂—SiO₂ bonding        chains) allowed in any direction; and also no D-D linkages (or        MO₂-MO₂ bonding chains) allowed along [001]. Subject to these        three properties, remaining D-D linkages are then permitted        along [010] and [100], which are second order only.        Additionally, N-doping will not significantly alter this        structure beyond only local effects.

In one embodiment the first layer of metal type (e.g. Al, Au, TiN, dopedpolysilicon, etc.) material exhibits the conducting properties of ametal.

In one embodiment the second layer of metal type (e.g. Al, Au, TiN,doped polysilicon, etc.) material exhibits the conducting properties ofa metal.

In one embodiment the single crystal tetragonal M_(x)N_(y)Si_(1-x)O₂(˜0.45≦x≦˜0.55; 0≦y≦˜0.05) wherein the elements M and Si are M=Zr|Hf orM=Hf and Zr—the material system may also contain small dopingconcentrations of elements N that do not alter the structuresignificantly or beyond locally but may replace M and/or Si in somesites or may exist as oxidised interstitials. N could be Y, Sc, Ti, Nb,Lu, Ta, C, Ge, N, Ga, or In. M_(x)N_(y)Si_(1-x)O₂ is completely mixedas-deposited. An important aspect of the invention is the translation ofthe dielectric local atomic structure to the expectant and resultantlocal and global electrical properties.

In one embodiment the insulator layer comprises a stable 3D crystallinesymmetric mix of single crystal tetragonal M_(x)N_(y)Si_(1-x)O₂(˜0.45≦x≦˜0.55; 0≦y≦˜0.05) wherein the elements M and Si are M=Zr|Hf orM=Hf and Zr—the material system may also contain small dopingconcentrations of elements N that do not alter the structuresignificantly or beyond locally but may replace M and/or Si in somesites or may exist as oxidised interstitials. N could be Y, Sc, Ti, Nb,Lu, Ta, C, Ge, N, Ga, or In. M_(x)N_(y)Si_(1-x)O₂ is completely mixedas-deposited.

In one embodiment the bonding chains between M and Si oxide elements aresymmetrically linked with each other in a three dimensional way suchthat no two same elements of M or Si are directly linked together along[001]; no two Si oxides are directly linked in any direction; and onlystaggered edge-linked MO₂ and SiO₂ chains are allowed along [001].Subject to these conditions, MO₂ linkages are permitted along [100] and[010] as second order bonding only.

In one embodiment the MO₈ dodecahedra and SiO₄ tetrahedra aresymmetrically linked with each other in a three dimensional way suchthat no two SiO₄ tetrahedra are directly linked together in anydirection. Similarly, no two MO₈ dodecahedra are directly linkedtogether along [001]. Only SiO₄ tetrahedra and MO₈ dodecahedra arelinked together along [001]. Subject to these conditions, MO₈dodecahedra can be linked together along [100] and [010] as second orderbonding only.

In one embodiment the as-deposited insulator layer comprises a singlecrystal tetragonal configuration to ensure symmetrical linkages.

In one embodiment the first layer of material comprises Al₂O₃.

In one embodiment the second layer of material comprises Al₂O₃.

In one embodiment the bulk-stable 3D tetragonal crystalline structuralproperties of MSiO₄ can be maintained when sandwiched between two layersof Al₂O₃ or two layers of metal.

In one embodiment the bonding chains between M and Si oxide elements aresymmetrically linked with each other in a three dimensional way suchthat no two same elements of M or Si are directly linked together along[001]; no two Si oxides are directly linked in any direction; and onlystaggered edge-linked MO₂ and SiO₂ chains are allowed along [001].Subject to these conditions, MO₂ linkages are permitted along [100] and[010] as second order bonding only.

In one embodiment the MO₈ dodecahedra and SiO₄ tetrahedra aresymmetrically linked with each other in a three dimensional way suchthat no two SiO₄ tetrahedra are directly linked together in anydirection. Similarly, no two MO₈ dodecahedra are directly linkedtogether along [001]. Only SiO₄ tetrahedra and MO₈ dodecahedra arelinked together along [001]. Subject to these conditions, MO₈dodecahedra can be linked together along [100] and [010] as second orderbonding only.

It will be appreciated that very slight local variations in thecrystalline structure can be accommodated provided they do not interactwith other local regions exhibiting slight variations or change theglobal crystalline planes—otherwise sites for global instability in thecrystal will form and grow, and grain boundaries will form through thechange in crystalline planes.

Given that the insulator is deposited in a tetragonal crystalline form,it will be appreciated that epitaxial growth of the insulator materialmay be achieved on appropriately lattice-matched crystalline substrates,either directly or by use of an intermediate lattice-buffer. This wouldopen up the possibility of epitaxial growth of the invention onsemiconductor substrates such as GaN, Si, Ge, Si_(x)Ge_(y), GaAs,In_(x)Ga_(1-x)As, etc.

Appropriate applications of the invention are Metal-Oxide-Semiconductor(MOS) devices, metal-in-silicon-oxide (MISO) devices, andMetal-Insulator-Metal (MIM) devices, employing these type ofsub-components at the core of their device operation, provided thatinterface reactions are prevented by careful consideration of thematerial systems in contact. When there is a possibility of interfacereactions, a very thin layer (˜0.5 nm thickness ≦˜1 nm) of Al₂O₃ can bedeposited to prevent interface reactions taking place.

Potential material systems and electronic applications are numerouswhere there is a need for a reliable, scalable, and stable high-kdielectric material that has a full set or subset of the followingproperties when compared to lower-k, wide band gap, dielectric materials(k≦9, e.g. SiO₂, SiO_(x)N_(y), Si_(x)N_(y), Al_(x)N_(y), Al₂O₃, etc.):high capacitance density for the equivalent thickness and area; lowoperating voltage leakage within a reasonable range (single dominantmechanisms at 0V—low ±V, low ±V to ±breakdown voltage); high breakdownfield within a reasonable range at 2× the operating voltage (with nosoft breakdown/stress events prior to hard breakdown); a quadraticvoltage coefficient of capacitance that is effectively zero (α≦|50-100|)for the un-doped bulk material, and not changing beyond this range withtemperature or frequency; low processing temperature; negligible chargetrapping and hysteresis; low capacitance dissipation; radiation hard;thickness scalability for low to high voltage applications; stabilityand reliability up to high processing temperatures (≦1050° C.); leads toincreased speed of devices; and reduced power consumption.

The following are among the many applications, but not limited, that canincorporate the invention such as analogue-digital-converters (ADCs);digital-analogue-converters (DACs); micro-electro-mechanical-systems(MEMS)/radio frequency (RF) switches; analogue mixed signal units;amplifiers; comparators; decouplers; MOS-based devices (MOSCAPs;MOSFETs: multi-gate devices, junctionless transistors, nanowires, etc.);epitaxial high-k oxide applications on metals, other oxides, orsemiconductors; automotive applications; reduced power requirementapplications such as portable devices; medical devices; applicationsrequiring the integration of analogue and digital components;applications that would benefit from reduced space requirements, reducedmaterial consumption, reduced energy/power consumption, and reducedcosts.

In one embodiment there is provided a Resistive Random Access Memory is(RRAM) device comprising an insulator material said insulator materialcomprises M_(x)N_(y)Si_(1-x)O₂ (˜0.45≦x≦˜0.55; 0≦y≦˜0.05) wherein theelements M and Si are M=Zr|Hf or M=Hf and Zr—the material system mayalso contain small doping concentrations of elements N that do not alterthe structure significantly or beyond locally but may replace M and/orSi in some sites or may exist as oxidised interstitials. N could be Y,Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In. M_(x)N_(y)Si_(1-x)O₂ iscompletely mixed as-deposited), wherein the bonding chains between M andSi oxide elements are symmetrically linked with each other in a threedimensional way such that no two same elements of M or Si are directlylinked together along [001]; no two Si oxides are directly linked in anydirection; and only staggered edge-linked MO₂ and SiO₂ chains areallowed along [001].

Subject to these conditions, MO₂ linkages are permitted along [100] and[010] as second order bonding only. The MO₈ dodecahedra and SiO₄tetrahedra are symmetrically linked with each other in a threedimensional way such that no two SiO₄ tetrahedra are directly linkedtogether in any direction. Similarly, no two MO₈ dodecahedra aredirectly linked together along [001]. Only SiO₄ tetrahedra and MO₈dodecahedra are linked together along [001]. Subject to theseconditions, MO₈ dodecahedra can be linked together along [100] and [010]as second order bonding only Within this structure Ti or other elementsare integrated into the matrix as N of y concentration in order toachieve the required RRAM properties.

In another embodiment there is provided a tunable capacitor devicecomprising an insulator material, said insulator material comprisesM_(x)N_(y)Si_(1-x)O₂ (˜0.45≦x≦˜0.55; 0≦y≦˜0.05) wherein the elements Mand Si are M=Zr|Hf or M=Hf and Zr—the material system may also containsmall doping concentrations of elements N that do not alter thestructure significantly or beyond locally but may replace M and/or Si insome sites or may exist as oxidised interstitials. N could be Y, Sc, Ti,Nb, Lu, Ta, C, Ge, N, Ga, or In. M_(x)N_(y)Si_(1-x)O₂ is completelymixed as-deposited), wherein the bonding chains between M and Si oxideelements are symmetrically linked with each other in a three dimensionalway such that no two same elements of M or Si are directly linkedtogether along [001]; no two Si oxides are directly linked in anydirection; and only staggered edge-linked MO₂ and SiO₂ chains areallowed along [001].

Subject to these conditions, MO₂ linkages are permitted along [100] and[010] as second order bonding only. The MO₈ dodecahedra and SiO₄tetrahedra are symmetrically linked with each other in a threedimensional way such that no two SiO₄ tetrahedra are directly linkedtogether in any direction. Similarly, no two MO₈ dodecahedra aredirectly linked together along [001]. Only SiO₄ tetrahedra and MO₈dodecahedra are linked together along [001]. Subject to theseconditions, MO₈ dodecahedra can be linked together along [100] and[010]. Within this structure Ti or other elements are integrated intothe matrix as N of y concentration in order to achieve the requiredvariation in alpha.

In a further embodiment of the present invention there is provided aninsulator material suitable for use in a capacitor or an electronicdevice, said material comprises M_(x)N_(y)Si_(1-x)O₂ (˜0.45≦x≦˜0.55;0≦y≦˜0.05) wherein the elements M and Si are M=Zr|Hf or M=Hf and Zr—thematerial system may also contain small doping concentrations of elementsN that do not alter the structure significantly or beyond locally butmay replace M and/or Si in some sites or may exist as oxidisedinterstitials. N could be Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In,wherein the elements M and Si are completely mixed as-deposited suchthat the insulator layer comprises staggered edge-linked SiO₂-MO₂bonding chains.

In another embodiment of the present invention there is provided amaterial comprising M_(x)N_(y)Si_(1-x)O₂ (˜0.45≦x≦˜0.55; 0≦y≦˜0.05)wherein the elements M and Si are M=Zr|Hf or M=Hf and Zr—the materialsystem may also contain small doping concentrations of elements N thatdo not alter the structure significantly or beyond locally but mayreplace M and/or Si in some sites or may exist as oxidisedinterstitials. N could be Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In,wherein the elements M and Si are mixed such that the insulator layercomprises staggered edge-linked SiO₂-MO₂ bonding chains to provide astable 3-dimensional single crystal system.

In one embodiment the insulator layer of material comprisesM_(x)N_(y)Si_(1-x)O₂, wherein 0.45≦x≦0.55 and 0≦y≦0.05, M comprises atleast one of Hf or Zr and N comprises at least one of Y, Sc, Ti, Nb, Lu,Ta, C, Ge, N, Ga, or In and further comprising Si.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more clearly understood from the followingdescription of an embodiment thereof, given by way of example only, withreference to the accompanying drawings, in which:

FIG. 1 illustrates a layered structure of a capacitor according to oneembodiment of the invention;

FIG. 2 illustrates a gate stack of a MOSFET device according to anotherembodiment of the invention;

FIG. 3 illustrates ball/stick (left), and Polyhedral (right) equivalentmodels (viewed in the [110] plane) of the tetragonal MSiO₄ (M=Hf|Zr)crystalline system according to the invention. FIG. 3 illustrates SiO₄tetrahedra (light gray), Si atoms (light grey); MO₈ dodecahedra (darkgrey), M atoms (dark grey); and O atoms (grey);

FIG. 4 illustrates a patterned MIM device that allows for direct contactto the top and bottom electrodes;

FIG. 5 illustrates capacitance density versus gate voltage at fivefrequencies for a prototype Si/SiO₂/Al/130 nm HfSiO₄/Al patterned MIMcapacitor;

FIG. 6 illustrates capacitance density hysteresis sweeps versus gatevoltage at 1 kHz for two devices of a prototype Si/SiO₂/Al/130 nmHfSiO₄/Al patterned MIM capacitor;

FIG. 7 illustrates capacitor quality factor (Q) versus gate voltage atfive frequencies for two devices of a prototype Si/SiO₂/Al/130 nmHfSiO₄/Al patterned MIM capacitor;

FIG. 8 illustrates Gate leakage current density versus gate voltage fortwo devices measured in different polarities from 0 V for a prototypeSi/SiO₂/Al/130 nm HfSiO₄/Al patterned MIM capacitor. Breakdown is seenat ˜±97 V. The kinks observed between ˜±70-90 V are measurementartefacts due to auto-range changing in the measurement instrument;

FIGS. 9 & 10 illustrates results achieved for a Dynamic Random AccessMemory device, according to another embodiment of the invention;

FIG. 11 illustrates at room temperature for a number of nano-scale MIMcapacitors (a) multi-frequency (1 kHz-100 kHz) capacitance-voltage dataover the voltage range ±40V; and (b) leakage current density versusvoltage over both polarities;

FIG. 12 illustrates at room temperature (a) capacitance equivalentthickness (CET) versus nominal film thickness, and (b) leakage currentdensity at estimated operating voltages—with electric breakdown fieldsversus MISO nominal thickness; and

FIG. 13 illustrates results confirming the radiation hard properties ofthe material of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to the drawings and initially FIG. 1, FIG. 1 shows a cutthrough section of the capacitor according to one embodiment of thepresent invention. The capacitor shown in FIG. 1 indicated generally bythe reference numeral 1 comprises a first layer of metal type material 2and a second layer of metal type material 3. An insulator layer ofmaterial 4 sandwiched between the first and second layers of the metaltype materials. The insulator layer 4 comprises crystalline tetragonalM_(x)Si_(1-x)O₂ (˜0.45≦x≦˜0.55) wherein the elements M and Si (M=Zr|Hfor M=Hf and Zr). The material system may also contain small dopingconcentrations of elements that do not alter the structure significantlybut may replace M and/or Si in some sites, or be present as interstitialoxides (e.g. Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In). The elementsM, Si and O are completely mixed as-deposited such that the insulatorlayer comprises throughout only staggered edge-linked SiO₂-MO₂ bondingchains along [001], or equivalently, only staggered edge-linked SiO₄tetrahedra (T) and MO₈ dodecahedra (D) along [001], i.e. only T-Dallowed along [001]. There are also no T-T linkages (or SiO₂—SiO₂bonding chains) allowed in any direction; and also no D-D linkages (orMO₂-MO₂ bonding chains) allowed along [001]. Subject to these threecritical properties, remaining D-D linkages are then permitted along[010] and [100] to second order bonding only.

FIG. 2 illustrates a gate stack of a MOSFET device according to anotherembodiment of the invention. The MOSFET device comprises a semiconductorlayer 10 and a dielectric layer 11. The dielectric layer can be a singleM_(x)Si_(1-x)O₂ layer, or a layer of M_(x)Si_(1-x)O₂ with a thin layerof Al₂O₃ between the M_(x)Si_(-x)O₂ layer and the semiconductor, ormetal gate, or both. A gate layer 12 is placed on top, the operation ofwhich is known in the art and does not need to be describer here.

FIG. 3 illustrates ball/stick (left), and Polyhedral (right) equivalentmodels (viewed in the [110] plane) of the tetragonal MSiO₄ (M=Hf|Zr)crystalline system according to the invention. FIG. 3 illustrates SiO₄tetrahedra (light gray), Si atoms (light grey); MO₈ dodecahedra (darkgrey), M atoms (dark grey); and O atoms (grey).

The invention involves the careful construction of single crystallinematerial systems to provide an effective zero alpha, effective high-k,highly stable MIM capacitor. Appropriate applications of the inventionare Analog-Digital-Converters (ADCs), Digital-Analog-Converters (DACs),Micro-Electro-Mechanical-System (MEMS) radio frequency (RF) switches forterrestrial and space applications. The material is effective at lowtemperature, and crucially either maintains or improves in performanceup to CMOS temperatures of ˜1,050° C.

The invention provides for the realization of a low deposition andprocessing temperature (T_(p)≦400° C.) material system for applicationin a metal-insulator-metal capacitor which yields a novel and tunablehigh effective k-value, zero effective alpha stable material stackexhibiting capacitance stability with voltage/frequency (a), andtemperature/frequency (α_(T),α_(f)). Alpha (α) is the quadratic voltagecoefficient of capacitance (a.k.a. QCC, VCC), and α_(T)/α_(f) is thetemperature and frequency coefficients of capacitance, respectively.

Binary high-k oxides (e.g. MO₂) generally give a positive polarity ofalpha, and covalent low-k binary oxides (e.g. SiO₂) generally give anegative polarity of alpha. For M_(x)Si_(1-x)O₂ (0<x<1), the onlybulk-stable and 3D-symmetric crystalline structure is x=0.5, a.k.a.MSiO₄ to within approximately x=0.5±0.05, but the interface of MSiO₄with a Si-based or an M-based material is unstable. Nevertheless, theinterface of MSiO₄ with Al₂O₃ or a metal is stable and therefore thebulk-stable 3D crystalline structural properties of MSiO₄ can bemaintained when sandwiched between two layers of Al₂O₃ or two layers ofmetal. The effective alpha of MSiO₄ is a summation between a negativealpha contribution from the SiO₂ in MSiO₄ and a positive alphacontribution from the MO₂ in MSiO₄, thus providing an approximately zeroalpha material. The interface of SiO₂/MO₂ is constantly in flux andprovides its own contribution to alpha (˜3×10²) while maintaining theindividual properties of SiO₂ and MO₂, ensuring the limited impact ofSiO₂/MO₂ laminate structures. The k-value of amorphous MSiO₄ is ˜12, butthe invention can achieve slightly higher k-values of 15-17 due to theglobal tetragonal crystalline symmetry of the MSiO₄ structure, giving anapproximate four times boost to the k-value for SiO₂ (—2.5× boost tosilicon nitrides and silicon oxynitrides) while maintaining a zeroalpha.

It also has very low leakage for a crystalline structure, a large bandgap, and a high breakdown field. A stable 3D crystalline globallysymmetric mix of MSiO₄, as shown in FIG. 3 reduces thermal expansioncompared to MO₂, and reduces the spatial variation of electronic chargecompared to MO₂.

Claims of a stable mix of amorphous or crystalline MO₂ (or ZrO₂) andamorphous/crystalline SiO₂ are erroneous, either in mixed format orlayered format, because such a mix is inherently unstable and unlesswell mixed as-deposited in the unique MSiO₄ (zircon/hafnon) tetragonalcrystalline configuration.

The single crystalline 3D crystalline structure of the present inventionensures an insulator material comprising M_(x)Si_(1-x)O₂ wherein thebonding chains between M and Si oxide elements are symmetrically linkedwith each other in a three dimensional way such that no two sameelements of M or Si are directly linked together along [001]; no two Sioxides are directly linked in any direction; and only staggerededge-linked MO₂ and SiO₂ chains are allowed along [001].

Subject to these conditions, MO₂ linkages are permitted along [100] and[010]. This is critical to the stability of the structure, as well as tothe low leakage, high breakdown, good k-value, and absolute alphaproperties of the material. This MIM structure forms a baseline for anMIM with a k-value of 15-17. This can then be used in an extendedstructure as described in more detail below.

It will be appreciated that applications of the invention greatlyenhance current analog device circuitry and provide a route to achievingreduced size, high speed, and lower operating voltage applications.Deposited and developed MSiO₄ MIMs and the initial results areoutstanding, confirming the predicted properties stated.

A summary of results to date for four different prototype sets are:k-value ˜15-17; α<|50| ppm/V²; Q>50; J(@V_(op))<1×10⁻⁷ A/cm²; E_(BV)˜6-8MV/cm (increasing with anneal); capacitance density(F/m²)=(k˜15-17)ε₀/t(in metres), where t is chosen as a balance betweenthe required capacitance density and the minimum electric fieldbreakdown permitted for the desired operating voltage.

FIG. 4 illustrates a patterned MIM device that allows for direct contactto the top and bottom electrodes using the insulating material accordingto one embodiment of the invention.

FIG. 5 illustrates capacitance density versus gate voltage at fivefrequencies for a prototype Si/SiO₂/Al/130 nm HfSiO₄/Al patterned MIMcapacitor;

FIG. 6 illustrates capacitance density hysteresis sweeps versus gatevoltage at 1 kHz for two devices of a prototype Si/SiO₂/Al/130 nmHfSiO₄/Al patterned MIM capacitor.

FIG. 7 illustrates capacitor quality factor (Q) versus gate voltage atfive frequencies for two devices of a prototype Si/SiO₂/Al/130 nmHfSiO₄/Al patterned MIM capacitor.

FIG. 8 illustrates gate leakage current density versus gate voltage fortwo devices measured in different polarities from 0 V for a prototypeSi/SiO₂/Al/130 nm HfSiO₄/Al patterned MIM capacitor. Breakdown is seenat ˜±97 V. The kinks observed between ˜±70-90 V are measurementartefacts due to auto-range changing in the measurement instrument.

The desired MSiO₄ growth structure of tetragonal symmetry globally canbe achieved using a co-pulsed (or traditional sequential metal pulse)plasma enhanced atomic layer deposition process at low temperature. Theprecursors that can be used are commercially availableTetrakis(ethlymethylamino) silane (TEMASi) andTetrakis(ethylmethylamino) hafnium/zirconium (TEMAHf/TEMAZr) althoughother alkyl amido precursors of the general formula (RR′N)₄Si and(RR′N)₄M, where R may or may not be equivalent to R′ could besubstituted. It will be appreciated that other sources of Si and HF canbe used

The process has four steps that are repeated in sequence; (1) pulsing ofSi and M precursors; (2) purging excess of these reagents to exhaust;(3) substrate exposure to a remote O₂/inert gas plasma; 4) purging ofresidual oxidant plasma.

It will be appreciated that state of the art has solid state switchesthat have poor RF performance, and mechanical switches that have good RFperformance but are costly, heavy, and bulky. These do not use high-kmaterials, and there are no MEMS RF switches available commerciallyusing high-k materials beyond a k˜6-7. Miniaturized MEMS RF capacitiveswitches without high-k are available and have better RF performance,light, and low cost.

However, charge trapping, stability and limited capacitance density(limited k-value) are major issues for performance. The inventionaddresses these bottleneck issues by providing a k of ˜15-17, negligiblecharge trapping and high stability with the low leakage, high breakdownvoltage, and high capacitance density. This will improve performance andallow for redundancy in the system.

In another embodiment of the invention there is provided aMetal-Insulator-Metal capacitor, as hereinbefore described, is adaptedfor use in resistive RAM and/or tuneable capacitor applications. Therealisation of a low processing temperature (T_(p)≦400° C.) materialsystem for application in a metal-insulator-metal capacitor provides anovel and stable high effective k-value material system exhibitingcapacitance and leakage characteristics suitable for resistive RAM andtuneable capacitor applications. This can be achieved by a plasmaenhanced atomic layer deposition process to achieve low temperaturegrowth, mix, stoichiometry, and concentration ratio of the materialsystem for testing and potential realisation of metal-insulator-metalcapacitor structures tailored for resistive RAM and tuneable capacitors.

The problem with current applications is that oxide materials that seemmost suitable for RRAM (predictable leakage pathways and breakdownfilaments) and tuneable capacitor (high capacitance variation withvoltage, or high α, systems susceptible to significant polarisation)applications are also highly variable systems in terms of theirelectrical properties and atomic structure.

Using the stability of this 3D crystalline structure the M cations arereplaced by Ti or Ti—O—Ti—or other elements instead of Ti that have ahigh polarisation in their oxide form—in low concentrations, and at welldistributed locations in the material structure. This placement allowscontrol of the interactions between these regions and maintains a stablestructural matrix around these regions, which can be referred to as“X-regions”. As described above the atomic structure ensures that theelectrical properties exhibit low leakage, high breakdown, except nowthe invention provides implanted regions that allows an increase thequadratic variation of capacitance with voltage.

For resistive RAM, it is necessary to maintain these stable propertiesduring post-breakdown operation, but engineer preferred filaments routesfor leakage and breakdown pathways to form. By creating X-regionsachieves preferential routes for these filaments to form withoutdestabilising the structure of the material system and the associatedvariability in the resistive properties of the device. The ResistiveRandom Access Memory (RRAM) device comprises an insulator layercomprising crystalline tetragonal M_(x)Si_(1-x)O₂ (˜0.45≦x≦˜0.55)wherein the elements M and Si (M=Zr|Hf or M=Hf and Zr—the materialsystem may also contain small doping concentrations of elements that donot alter the structure significantly but may replace M and/or Si insome sites, or exist as oxidised interstitials, e.g. Y, Sc, Ti, Nb, Lu,Ta, C, Ge, N, Ga, or In) are completely mixed as-deposited such that theinsulator layer comprises throughout only staggered edge-linked SiO₂-MO₂bonding chains along [001], or equivalently, only staggered edge-linkedSiO₄ tetrahedra (T) and MO₈ dodecahedra (D) along [001], i.e. only T-Dallowed along [001]. There are also no T-T linkages (or SiO₂—SiO₂bonding chains) allowed in any direction; and also no D-D linkages (orMO₂-MO₂ bonding chains) allowed along [001]. Subject to these threecritical properties, remaining D-D linkages are then permitted along[010] and [100]. Within this configuration it is possible to engineerthe addition of one or more metal elements to form regions that providefor leakage and/or breakdown pathways in said 3D crystalline matrix.

In another embodiment there is provided a tunable capacitor devicecomprising an insulator material, said insulator layer comprisescrystalline tetragonal M_(x)Si_(1-x)O₂ (˜0.45≦x≦˜0.55) wherein theelements M and Si (M=Zr|Hf or M=Hf and Zr—the material system may alsocontain small doping concentrations of elements that do not alter thestructure significantly but may replace M and/or Si in some sites, orexist as oxidised interstitials, e.g. Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N,Ga, or In) are completely mixed as-deposited such that the insulatorlayer comprises throughout only staggered edge-linked SiO₂-MO₂ bondingchains along [001], or equivalently, only staggered edge-linked SiO₄tetrahedra (T) and MO₈ dodecahedra (D) along [001], i.e. only T-Dallowed along [001]. There are also no T-T linkages (or SiO₂—SiO₂bonding chains) allowed in any direction; and also no D-D linkages (orMO₂-MO₂ bonding chains) allowed along [001]. Subject to these threecritical properties, remaining D-D linkages are then permitted along[010] and [100]. Within this configuration it is possible to engineerthe addition of one or more metal elements to define at least one regionof high polarisation within the stable 3D crystalline matrix. Fortuneable capacitance, it is again necessary to maintain these stableproperties, but operation for this application will be pre-breakdown andnot post-breakdown as for RRAM. The X-regions will create regions ofhigh polarisation but within a stable matrix. The stable matrix willallow for a degree of stable electrical behaviour while allowing theincrease in capacitor variation with voltage as well as the effectivek-value of the system due to the inclusion of the ultra high-kX-regions.

In a further embodiment the invention can be used in applications forDynamic Random Access Memory (DRAM). FIGS. 9 and 10 illustrates resultsachieved using a 2 nm thick film sandwiched between Ti and TiW showbreakdown fields between 7-8 MV/cm in both polarities. Leakage was foundto be ˜±10⁻⁶-˜±10⁻⁸ depending on the selected operating voltage.Capacitance density at 0V and from 1 kHz to 1 MHz was measured at ˜55-67fF/μm² for the 100 μm×100 μm and 100 μm×50 μm area capacitors (>>10fF/μm²). Linearity is not obtained at this thickness and is not aprimary objective for DRAM applications. The equivalent oxide thicknessis ˜0.5 nm. Leakage in the positive gate voltage polarity can beimproved by at least one order of magnitude by using a differentelectrode, such as Ti or TiN. The k-value of the thin film is estimatedto be 16-17. The device can be optimised for different DRAMapplications.

The devices analysed at room temperature in FIG. 11 had ˜130 nm ofmetal-in-silicon-oxide (MISO) deposited on an in-house sputtered Al(˜500 nm). The top electrode was deposited using a gentle process ofsputtered Al (˜500 nm) and patterned by lift-off (area=1×10⁻⁸ m²).C_(D)˜1 fF/μm² (QCC˜15 ppm/V², capacitor quality factor (Q)>50), withE_(BD)˜7.5 MV/cm and J˜2×10⁻⁸ A/cm² at V_(op)=±30 V is achieved. It isgenerally possible to obtain such linear QCC values due to the nature ofthe MISO material system, although metal interface-optimisation isessential for thin film MIMCAPS with d<˜50 nm. No significant bulk orinterfacial charge trapping is observed (not shown). These MIMCAPS wereprimarily assessed for suitability to RF MEMS applications.

FIG. 12 shows: (a) capacitance equivalent thicknesses (CET), with linearfits to obtain an extracted MISO k-value estimate; and (b) leakagecurrent densities at estimated operating voltages, with electricbreakdown fields. These properties are plotted versus MISO nominalthickness. As-deposited and high temperature annealed samples, employinga variety of different top and bottom electrodes, are included withinthe analysis shown in FIG. 12, demonstrating that the optimum structurecan be achieved in the as-deposited state. Linear scaling from ˜350 nmto ˜2 nm of the MISO MIMCAPS is a particularly unique achievement for ahigh-k dielectric system, and linear fits give an extracted MISO k-valueestimate of ˜17, which concurs well with the MIMCAPS' individual k-valueextractions. Low leakage current densities at estimated operatingvoltages are achieved—along with high electrical breakdown fields,providing uniform results across the thickness range, showingscalability, temperature stability, and considerably improved combinedproperties compared to other high-k dielectric MIMCAPS when a k-value of˜17 is achieved compared to ˜10 by the best alternative non-scalablelaminate methods. Such combined properties, along with temperaturestability, a linear QCC, and a high Q-value (not shown), are desirablefor a wide range of analog-based applications. The results shown in FIG.12 illustrate excellent repeatability; linear CET v thickness; Extractedk-value ˜17; Capacitance linearity and provides a non-ideal interface.

It will be appreciated that the un-doped Hf-based invention providesstable, tailored, expected radiation-hard high-k (˜17) MIMs with thefollowing properties:

-   -   ˜2.5× Increase in Si_(x)N_(y) or Si_(x)O_(y)N, capacitance        density.    -   No significant charge trapping.    -   Scalable to any thickness, thick or thin film.    -   Low leakage current density (<˜1-5×10⁻⁸ A/cm² for V_(op)).    -   High breakdown electric field 7.5 MV/cm).    -   Excellent bulk linearity with voltage/temperature/frequency        (|α|<˜50-100 units).    -   CMOS temperature processing compatibility (≦1050° C.) removing        bottleneck to integration of passives with CMOS.

FIG. 13 confirms the radiation hard properties of the material of thepresent invention, shown for an operating voltage=40V; MTTF similar forboth samples; Lifetime at 40V is ˜1-3 k years. As can be seen nodegradation after irradiation occurs.

It will be appreciated that where M is defined above other elements Nthat may dope or replace a small number of sites can be provided. Forexample, a small number of Si sites could have Ge, or a small number ofM sites could have Y, also Hf and Zr could both be present in thestructure and are interchangeable. N could also be an oxidisedinterstitial.

In the specification the term ‘metal type material’ encompasses puremetal, metal alloys, and heavily doped poly Si materials, all having theconductive properties of a metal and should be afforded the widestpossible interpretation in the contest of the present invention.

In the specification the terms “comprise, comprises, comprised andcomprising” or any variation thereof and the terms include, includes,included and including” or any variation thereof are considered to betotally interchangeable and they should all be afforded the widestpossible interpretation and vice versa.

The invention is not limited to the embodiments hereinbefore describedbut may be varied in both construction and detail.

1. A capacitor device comprising a first layer of material; a secondlayer of material; an insulator layer of material sandwiched between thefirst and second layers of the metal type materials, said insulatorlayer comprise m_(x)Si_(1-x)O₂, wherein the elements M and Si are mixedsuch that the insulator layer comprises staggered edge-linked SiO₂-MO₂bonding chains to provide a stable 3-dimensional single crystal system.2. The capacitor device of claim 1 wherein the bonding chains between Mand Si oxide elements are symmetrically linked with each other in athree dimensional way such that no two same elements of M or Si aredirectly linked together.
 3. The capacitor device as claimed in claim 1wherein the bonding chains between M and Si oxide elements aresymmetrically linked with each other in a three dimensional way suchthat no two same elements of M or Si are directly linked together in the(001) direction and no two Si oxides are directly linked in anydirection.
 4. The capacitor device as claimed in claim 1 wherein theelements M and Si are completely mixed as-deposited such that theinsulator layer comprises only staggered edge-linked SiO₄ tetrahedra (T)and MO₈ dodecahedra (D).
 5. The capacitor device as claimed in claim 1wherein M comprises Hafnium and/or zirconium.
 6. The capacitor device asclaimed in claim 1 wherein the insulator layer of material comprisesM_(x)N_(y)Si_(1-x)O₂, wherein 0.45≦x≦0.55 and 0≦y≦0.05, M comprises atleast one of Hf or Zr and N comprises at least one of Y, Sc, Ti, Nb, Lu,Ta, C, Ge, N, Ga, or In and further comprising SiMxN_(y)Si_(1-x)O2. 7.The capacitor device of claim 1 wherein the insulator layer comprises astable 3D single crystal tetragonal symmetric mix ofM_(x)N_(y)Si_(1-x)O₂, wherein 0.45≦x≦0.55 and 0≦y≦0.05, and comprisingof the elements M (Hf and/or Zr), N (Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N,Ga, or In) and Si.
 8. The capacitor device of claim 1 wherein theinsulator layer comprises a tetragonal single crystal configuration toensure symmetrical linkages between elements.
 9. The capacitor device ofclaim 1 wherein the first layer of material comprises Al₂O₃.
 10. Thecapacitor device of claim 1 wherein the second layer of materialcomprises Al₂O₃.
 11. The capacitor device of claim 9 wherein thebulk-stable 3D single crystal structural properties of MSiO₄ is adaptedto be maintained when sandwiched between two layers of Al₂O₃ or twolayers of metal.
 12. A Metal-Oxide-Semiconductor (MOS) device comprisingan insulating material, said insulator layer comprises M_(x)Si_(1-x)O₂wherein the oxides of the elements M and Si are completely mixedas-deposited such that the insulator layer comprises staggerededge-linked SiO₂-MO₂ bonding chains to provide a stable 3-dimensionalsingle crystal system.
 13. A Resistive Random Access Memory (RRAM)device comprising an insulator material, said insulator materialcomprises M_(x)Si_(1-x)O₂ wherein the elements M and Si are mixed suchthat the insulator layer comprises staggered SiO₂-MO₂ bonding chains toform a stable 3D crystalline matrix and mixed with one or more metalelements to form regions that provide for leakage and/or breakdownpathways in the 3D crystalline matrix.
 14. A Resistive Random AccessMemory (RRAM) device of claim 13 wherein the one or more metal elementscomprise at least one of Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In. 15.A Resistive Random Access Memory (RRAM) device as claimed in claim 13wherein the insulator layer of material comprises MN_(y)Si_(1-x)O₂,wherein 0.45≦x≦0.55 and 0≦y≦0.05, M comprises at least one of Hf or Zrand N comprises at least one of Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, orIn and further comprising SiMxN_(y)Si_(1-x)O₂.
 16. A tunable capacitordevice comprising an insulator material, said insulator materialcomprises M_(x)Si_(1-x)O₂ wherein the elements M and Si are mixed suchthat the insulator layer comprises staggered SiO₂-MO₂ bonding chains toform a stable 3D crystalline matrix and mixed with one or more metalelements to define at least one region of high polarisation within thestable 3D crystalline matrix.
 17. A tunable capacitor device of claim 16wherein the one or more metal elements comprise at least one of Y, Sc,Ti, Nb, Lu, Ta, C, Ge, N, Ga, or In.
 18. A tunable capacitor device asclaimed in claim 16 wherein the insulator layer of material comprisesM_(x)N_(y)Si_(1-x)O₂, wherein 0.45≦x≦0.55 and 0≦y≦0.05, M comprises atleast one of Hf or Zr and N comprises at least one of Y, Sc, Ti, Nb, Lu,Ta, C, Ge, N, Ga, or In and further comprising SiMxN_(y)Si_(1-x)O2. 19.The capacitor device of claim 10 wherein the bulk-stable 3D singlecrystal structural properties of MSiO₄ is adapted to be maintained whensandwiched between two layers of Al₂O₃ or two layers of metal.
 20. AResistive Random Access Memory (RRAM) device as claimed in claim 14wherein the insulator layer of material comprises M_(x)N_(y)Si_(1-x)O₂,wherein 0.45≦x≦0.55 and 0≦y≦0.05, M comprises at least one of Hf or Zrand N comprises at least one of Y, Sc, Ti, Nb, Lu, Ta, C, Ge, N, Ga, orIn and further comprising SiMxN_(y)Si_(1-x)O2.